The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 03, 2007
Filed:
Jun. 04, 2004
Hiroaki Hazama, Hachioji, JP;
Seiichi Mori, Tokyo, JP;
Hirohisa Iizuka, Yokkaichi, JP;
Norio Ootani, Yokkaichi, JP;
Kazuhito Narita, Yokkaichi, JP;
Hiroaki Hazama, Hachioji, JP;
Seiichi Mori, Tokyo, JP;
Hirohisa Iizuka, Yokkaichi, JP;
Norio Ootani, Yokkaichi, JP;
Kazuhito Narita, Yokkaichi, JP;
Kabushiki Kaisha Toshiba, Tokyo, JP;
Abstract
A nonvolatile semiconductor memory device including at least one MOS transistor in a peripheral circuit comprises a semiconductor substrate, isolation insulating films for defining a plurality of element formation regions, each of the isolation insulating films being buried in an isolation trench provided in the semiconductor substrate, a floating gate provided in each of the element formation regions via a first gate insulating film, a control gate provided on the floating gate via a second gate insulating film, and source and drain regions provided in the semiconductor substrate in self-alignment with the control gate, wherein the floating gate is self-aligned at an isolation end in a direction of a channel width, and comprises a plurality of polysilicon films.