The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7234412 B1

PDF
Full Text
Expired
Date of Patent:
Jun. 26, 2007

Filed:

Jan. 23, 2003
Applicants:

Craig M. Carpenter, Boise, ID (US);

Ross S. Dando, Nampa, ID (US);

Philip H. Campbell, Meridian, ID (US);

Allen P. Mardian, Boise, ID (US);

Gurtej S. Sandhu, Boise, ID (US);

Inventors:

Craig M. Carpenter, Boise, ID (US);

Ross S. Dando, Nampa, ID (US);

Philip H. Campbell, Meridian, ID (US);

Allen P. Mardian, Boise, ID (US);

Gurtej S. Sandhu, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
C23C 16/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method includes removing at least a piece of a deposition chamber liner from a deposition chamber by passing it through a passageway to the deposition chamber through which semiconductor substrates pass into and out of the chamber for deposition processing. A replacement for the removed deposition chamber liner piece is provided into the chamber by passing the replacement through said passageway. A liner apparatus includes a plurality of pieces which when assembled within a selected semiconductor substrate deposition processor chamber are configured to restrict at least a majority portion of all internal wall surfaces which define said semiconductor substrate deposition processor chamber from exposure to deposition material within the chamber. At least some of the pieces are sized for passing completely through a substrate passageway to the chamber through which semiconductor substrates pass into and out of the chamber for deposition processing.


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