The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 12, 2007
Filed:
Jan. 06, 2004
David V. Horak, Essex Junction, VT (US);
Toshiharu Furukawa, Essex Junction, VT (US);
Akihisa Sekiguchi, Briarcliff Manor, NY (US);
David V. Horak, Essex Junction, VT (US);
Toshiharu Furukawa, Essex Junction, VT (US);
Akihisa Sekiguchi, Briarcliff Manor, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method of forming a doped gate structure on a semiconductor device and a semiconductor structure formed in that method are provided. The method comprises the steps of providing a semiconductor device including a gate dielectric layer, and forming a gate stack on said dielectric layer. This latter step, in turn, includes the steps of forming a first gate layer on the dielectric layer, and forming a second disposable layer on top of the first gate layer. A fat spacer is formed round the first gate layer and the second disposable layer. The second disposable layer is removed, and ions are implanted in the first gate layer to supply additional dopant into the gate above the gate dielectric layer, while the fat disposable spacer keeps the implanted ions away from the critical source and drain diffusion regions.