The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 05, 2007
Filed:
May. 13, 2004
Bruce Querbach, Orangevale, CA (US);
Amjad Khan, Folsom, CA (US);
Mike Tripp, Forest Grove, OR (US);
Luis Briceno Guerrero, San Jose, CR;
Marco A. Vindas Vargas, San Jose, CR;
Ali Muhtaroglu, Hillsboro, OR (US);
Bruce Querbach, Orangevale, CA (US);
Amjad Khan, Folsom, CA (US);
Mike Tripp, Forest Grove, OR (US);
Luis Briceno Guerrero, San Jose, CR;
Marco A. Vindas Vargas, San Jose, CR;
Ali Muhtaroglu, Hillsboro, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Embodiments of the invention provide a logic simulation having a controllable delay model implemented therein that may be used to validate AC I/O loopback design in a pre-silicon environment by introducing delay models that allow the logic simulators to simulate analog behavior. For one embodiment of the invention, a fixed processor ratio is selected and delay statements of the hardware description language correspond to a specific time delay. These fixed values provide the ability to accurately determine and adjust delay in an analog simulation.