The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 05, 2007

Filed:

Nov. 15, 2004
Applicants:

Sergey D. Lopatin, Santa Clara, CA (US);

Robert Fiordalice, Austin, TX (US);

Faivel Pintchovski, Austin, TX (US);

Igor Ivanov, Dublin, CA (US);

Wen Z. Kong, Newark, CA (US);

Artur Kolics, Dublin, CA (US);

Inventors:

Sergey D. Lopatin, Santa Clara, CA (US);

Robert Fiordalice, Austin, TX (US);

Faivel Pintchovski, Austin, TX (US);

Igor Ivanov, Dublin, CA (US);

Wen Z. Kong, Newark, CA (US);

Artur Kolics, Dublin, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/4763 (2006.01);
U.S. Cl.
CPC ...
Abstract

An integrated circuit and a method of manufacturing an integrated circuit is provided including providing an integrated circuit having a trench and via provided in a dielectric layer. A nano-electrode-array is formed over the dielectric layer in the trench and via, and a conductor is deposited over the nano-electrode-array. The conductor and the nano-electrode-array are coplanar with a surface of the dielectric layer.


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