The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 29, 2007

Filed:

Nov. 02, 2004
Applicants:

Hiroshi Kujirai, Kunitachi, JP;

Kousuke Okuyama, Kawagoe, JP;

Kazuhiro Hata, Akishima, JP;

Kiyonori Oyu, Ome, JP;

Ryo Nagai, Nishitama, JP;

Hiroyuki Uchiyama, Tachikawa, JP;

Takahiro Kumauchi, Hamura, JP;

Teruhisa Ichise, Ome, JP;

Inventors:

Hiroshi Kujirai, Kunitachi, JP;

Kousuke Okuyama, Kawagoe, JP;

Kazuhiro Hata, Akishima, JP;

Kiyonori Oyu, Ome, JP;

Ryo Nagai, Nishitama, JP;

Hiroyuki Uchiyama, Tachikawa, JP;

Takahiro Kumauchi, Hamura, JP;

Teruhisa Ichise, Ome, JP;

Assignee:

Elpida Memory, Inc., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01);
U.S. Cl.
CPC ...
Abstract

Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET: Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented.


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