The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 29, 2007
Filed:
Feb. 10, 2005
Douglas J. Bonser, Hopewell Junction, NY (US);
Srikanteswara Dakshina-murthy, Wappingers Falls, NY (US);
Mark C. Kelling, Marlboro, NY (US);
John G. Pellerin, Hopewell Junction, NY (US);
Johannes F. Groschopf, Fishkill, NY (US);
Edward Asuka Nomura, Poughkeepsie, NY (US);
Douglas J. Bonser, Hopewell Junction, NY (US);
Srikanteswara Dakshina-Murthy, Wappingers Falls, NY (US);
Mark C. Kelling, Marlboro, NY (US);
John G. Pellerin, Hopewell Junction, NY (US);
Johannes F. Groschopf, Fishkill, NY (US);
Edward Asuka Nomura, Poughkeepsie, NY (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
A method of forming a shallow trench isolation (STI) region in a silicon substrate creates an STI region that extends above a top surface of the silicon substrate. A planarizing dielectric layer is formed on the substrate and extends above the field oxide regions. The planarizing dielectric layer is removed by chemical mechanical polishing or blanket etch back, for example, as well as those portions of the field oxide regions that extend above the top surface of the substrate and the active regions. The step height is thereby eliminated or significantly reduced.