The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 22, 2007
Filed:
Jan. 29, 2004
Yuji Wada, Tachikawa, JP;
Susumu Kasukabe, Yokohama, JP;
Takehiko Hasebe, Yokohama, JP;
Yasunori Narizuka, Hiratsuka, JP;
Akira Yabushita, Yokohama, JP;
Terutaka Mori, Urayasu, JP;
Akio Hasebe, Kodaira, JP;
Yasuhiro Motoyama, Kodaira, JP;
Teruo Shoji, Mitaka, JP;
Masakazu Sueyoshi, Kodaira, JP;
Yuji Wada, Tachikawa, JP;
Susumu Kasukabe, Yokohama, JP;
Takehiko Hasebe, Yokohama, JP;
Yasunori Narizuka, Hiratsuka, JP;
Akira Yabushita, Yokohama, JP;
Terutaka Mori, Urayasu, JP;
Akio Hasebe, Kodaira, JP;
Yasuhiro Motoyama, Kodaira, JP;
Teruo Shoji, Mitaka, JP;
Masakazu Sueyoshi, Kodaira, JP;
Renesas Technology Corp., Tokyo, JP;
Abstract
The fabrication of a semiconductor integrated circuit device involves testing using a pushing mechanism that is constructed by forming, over the upper surface of a thin film probe, a reinforcing material having a linear expansion coefficient (thermal expansion coefficient) almost equal to that of a wafer to be tested; forming a groove in the reinforcing material above a contact terminal; placing an elastomer in the groove so that a predetermined amount projects out of the groove; and disposing a pusher and another elastomer to sandwich the pusher between the elastomers. With the use of such a probe, it is possible to improve the throughput of wafer-level electrical testing of a semiconductor integrated circuit.