The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 15, 2007
Filed:
Apr. 01, 2004
Steven M. Trimberger, San Jose, CA (US);
Shekhar Bapat, Cupertino, CA (US);
Robert W. Wells, Cupertino, CA (US);
Robert D. Patrie, Scotts Valley, CA (US);
Andrew W. Lai, Fremont, CA (US);
Steven M. Trimberger, San Jose, CA (US);
Shekhar Bapat, Cupertino, CA (US);
Robert W. Wells, Cupertino, CA (US);
Robert D. Patrie, Scotts Valley, CA (US);
Andrew W. Lai, Fremont, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
Described are methods for implementing customer designs in programmable logic devices (PLDs). The defect tolerance of these methods makes them particularly useful with the adoption of 'nanotechnology' and molecular-scale technology, or 'molectronics.' Test methods identify alternative physical interconnect resources for each net required in the user design and, as need, reroute certain signal paths using the alternative resources. The test methods additionally limit testing to required resources so devices are not rejected as a result of testing performed on unused resources. The tests limit functional testing of used resources to those functions required in the user designs.