The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 15, 2007
Filed:
Sep. 27, 2001
Lifeng Wu, San Jose, CA (US);
Jeong Y. Choi, Portland, OR (US);
Alvin I. Chen, San Jose, CA (US);
Jingkun Fang, Santa Clara, CA (US);
Lifeng Wu, San Jose, CA (US);
Jeong Y. Choi, Portland, OR (US);
Alvin I. Chen, San Jose, CA (US);
Jingkun Fang, Santa Clara, CA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
The present invention is directed to methods for reliability simulations in aged circuits whose operation has been degraded through hot-carrier or other effects by allowing design rules on degradation to be included in the netlist. Once the hot-carrier circuit simulation is launched, the rules are checked and the reliability design rule violations are reported. The process can be performed on either the layout or schematic window. The design rule criteria can be any device parameter and can be expressed in absolute or relative terms. The criteria can be based on device type, model card name, instance geometry, or temperature. Additionally, values can be set prior to beginning the simulation.