The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 15, 2007
Filed:
Jun. 07, 2004
Masahiko Ogino, Hitachi, JP;
Takumi Ueno, Mito, JP;
Shuji Eguchi, Tokai-mura, JP;
Akira Nagai, Hitachi, JP;
Toshiya Satoh, Kanasagou-machi, JP;
Toshiaki Ishii, Hitachi, JP;
Hiroyoshi Kokaku, Hitachi, JP;
Tadanori Segawa, Hitachi, JP;
Nobutake Tsuyuno, Hitachi, JP;
Asao Nishimura, Kokubunji, JP;
Ichiro Anjoh, Koganei, JP;
Masahiko Ogino, Hitachi, JP;
Takumi Ueno, Mito, JP;
Shuji Eguchi, Tokai-mura, JP;
Akira Nagai, Hitachi, JP;
Toshiya Satoh, Kanasagou-machi, JP;
Toshiaki Ishii, Hitachi, JP;
Hiroyoshi Kokaku, Hitachi, JP;
Tadanori Segawa, Hitachi, JP;
Nobutake Tsuyuno, Hitachi, JP;
Asao Nishimura, Kokubunji, JP;
Ichiro Anjoh, Koganei, JP;
Renesas Technology Corp., Tokyo, JP;
Abstract
Semiconductor devices,-semiconductor wafers, and semiconductor modules are provided: wherein the semiconductor device has a small warp; damages at chip edge and cracks in a dropping test are scarcely generated; and the semiconductor device is superior in mounting reliability and mass producibility. The semiconductor devicecomprising: a semiconductor chipa porous stress relaxing layerprovided on the plane, whereon circuits and electrodes are formed, of the semiconductor chip; a circuit layerprovided on the stress relaxing layer and connected to the electrodes; and external terminalsprovided on the circuit layer; wherein an organic protecting filmis formed on the plane, opposite to the stress relaxing layer, of the semiconductor chip, and respective side planes of the stress relaxing layer, the semiconductor chipand the protecting filmare exposed outside on a same plane.