Sram memories and microprocessors having logic portions implemented in high-performance silicon substrates and sram array portions having field effect transistors with linked bodies and method for making same

Abstract

The present invention generally concerns fabrication methods and device architectures for use in memory circuits, and more particularly concerns hybrid silicon-on-insulator (SOI) and bulk architectures for use in memory circuits. Once aspect of the invention concerns CMOS SRAM cell architectures where at least one pair of adjacent NFETs in an SRAM cell have body regions linked by a leakage path diffusion region positioned beneath shallow source/drain diffusions, where the leakage path diffusion region extends from the bottom of the source/drain diffusion to the buried oxide layer, and at least one pair of NFETs from adjacent SRAM cells which have body regions linked by a similar leakage path diffusion region beneath adjacent source/drain diffusions. Another aspect of this invention concerns a microprocessor fabricated on an hybrid orientation substrate where the logic portion of the circuit has NFETs fabricated in (100) crystal orientation SOI silicon regions with floating body regions and PFETs fabricated in (110) crystal orientation bulk silicon regions; and where the SRAM memory portion has NFETs fabricated in (100) crystal orientation SOI silicon regions with body regions linked by leakage path diffusion regions beneath shallow source/drain diffusions and PFETs fabricated in (110) crystal orientation silicon regions.