The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 08, 2007
Filed:
Feb. 22, 2005
Shih-ked Lee, Fremont, CA (US);
Chuen-der Lien, Los Altos Hills, CA (US);
Louis Huang, San Jose, CA (US);
Gaolong Jin, Hillsboro, OR (US);
Wanqing Cao, Portland, OR (US);
Guo-qiang Lo, Singapore, SG;
Shih-Ked Lee, Fremont, CA (US);
Chuen-Der Lien, Los Altos Hills, CA (US);
Louis Huang, San Jose, CA (US);
Gaolong Jin, Hillsboro, OR (US);
Wanqing Cao, Portland, OR (US);
Guo-Qiang Lo, Singapore, SG;
Integrated Device Technology, Inc., San Jose, CA (US);
Abstract
The present invention includes SRAM memory cells and methods for forming SRAM cells having reduced soft error rate. The SRAM cell includes a first NMOS transistor and a first PMOS transistor having a common gate, and a second NMOS transistor and a second PMOS transistor having a common gate. A first resistor is electrically coupled on one end to the drains of the first PMOS transistor and the first NMOS transistor; and is electrically coupled on the other end to the common gate of the second NMOS and second PMOS transistors. A second resistor is electrically coupled on one end to the drains of the second PMOS transistor and the second NMOS transistor; and is electrically coupled on the other end to the common gate of the first NMOS transistor and the first PMOS transistor. The added resistor can be embedded in a contact opening such that it does not take up valuable surface area on the semiconductor substrate. Thereby, data loss from soft errors can be avoided while preserving small memory cell size.