The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 01, 2007
Filed:
Mar. 30, 2004
Yew Wee Cheong, Penang, MY;
Yew Wee Cheong, Penang, MY;
Intel Corporation, Santa Clara, CA (US);
Abstract
Methods for grinding low-K interlayer dielectric (ILD) wafers are described herein. In various embodiments, the method may include cutting and severing a semiconductor wafer into a plurality of portions, the cutting and severing being performed in a manner that allows the portions to remain disposed with each other as if the semiconductor wafer had not been cut, applying a tape to a front side of the as if uncut semiconductor wafer, and grinding a backside of the taped as if uncut semiconductor wafer. In various other embodiments, the method may include attaching an adhesive to a backside of the semiconductor wafer prior to cutting the semiconductor wafer along the streets of the semiconductor wafer with the scribed lines to cut and sever the semiconductor wafer into a plurality of portions, with the portions remaining proximally disposed to each other and held in place by the adhesive as if the semiconductor device had not been cut.