Memory device with rapid word line switch

Abstract

A memory device includes an array of storage cells, multiple words lines, where each word line corresponds to a row in the array of storage cells, and multiple bit lines, where each bit line corresponds to a column in the array of storage cells. The device further includes a row decoder attached to the multiple word lines. The row decoder is operable to assert and to de-assert individual word lines. Each of the word lines has a head portion adjacent to where the word line is attached to the row decoder. The memory device supports a column decode sequence for accessing multiple storage cells within a row of the array. The column decode sequence both commences and terminates at or near the head portion of the word line corresponding to the row.