The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 24, 2007
Filed:
Nov. 15, 2004
Hung-wei Chen, Hsinchu, TW;
Ping-kun Wu, Hsin-Chu, TW;
Chao-hsiung Wang, Hsin-Chu, TW;
Fu-liang Yang, Hsin-Chu, TW;
Chenming HU, Alamo, CA (US);
Hung-Wei Chen, Hsinchu, TW;
Ping-Kun Wu, Hsin-Chu, TW;
Chao-Hsiung Wang, Hsin-Chu, TW;
Fu-Liang Yang, Hsin-Chu, TW;
Chenming Hu, Alamo, CA (US);
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
In preferred embodiments of the present invention, a method of forming CMOS devices using SOI and hybrid substrate orientations is described. In accordance with a preferred embodiment, a substrate may have multiple crystal orientations. One logic gate in the substrate may comprise at least one N-FET on one crystal orientation and at least one P-FET on another crystal orientation. Another logic gate in the substrate may comprise at least one N-FET and at least one P-FET on the same orientation. Alternative embodiments further include determining the preferred cleavage planes of the substrates and orienting the substrates relative to each other in view of their respective preferred cleavage planes. In a preferred embodiment, the cleavage planes are not parallel.