The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 24, 2007
Filed:
Oct. 16, 2003
Jung-chih Tsao, Hsin-Chu, TW;
Chi-wen LI, Hsinchu, TW;
Kei-wei Chen, Yonghe, TW;
Jye-wei Hsu, Hsinchu, TW;
Hsien-pin Fong, Yonghe, TW;
Steven Lin, Taipei, TW;
Ray Chuang, Taipei, TW;
Jung-Chih Tsao, Hsin-Chu, TW;
Chi-Wen Li, Hsinchu, TW;
Kei-Wei Chen, Yonghe, TW;
Jye-Wei Hsu, Hsinchu, TW;
Hsien-Pin Fong, Yonghe, TW;
Steven Lin, Taipei, TW;
Ray Chuang, Taipei, TW;
Taiwan Semiconductor Manufacturing Company, Hsin-Chu, TW;
Abstract
A method of forming a copper interconnect in an opening within a pattern is described. The copper interconnect has an Rs that is nearly independent of opening width and pattern density. A first copper layer having a concave upper surface and thickness tis formed in a via or trench in a dielectric layer by depositing copper and performing a first CMP step. A second copper layer with a thickness twhere t≦tand having a convex lower surface is deposited on the first copper layer by a selective electroplating method. The first and second copper layers are annealed and then a second CMP step planarizes the second copper layer to become coplanar with the dielectric layer. The invention is also a copper interconnect comprised of the aforementioned copper layers where the first copper layer has a grain density (G)≧Gfor the second copper layer.