The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 24, 2007

Filed:

Jan. 16, 2002
Applicant:

Valery V. Felmetsger, Goleta, CA (US);

Inventor:

Valery V. Felmetsger, Goleta, CA (US);

Assignee:

Tegal Corporation, Petaluma, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/20 (2006.01);
U.S. Cl.
CPC ...
Abstract

A plurality of successive layers are firmly adhered to one another and to a wafer surface and an electrical component or sub-assembly even when the wafer surface is not even and the layers are bent. The wafer surface is initially cleaned by an ion bombardment of an inert gas (e.g. argon) on the wafer surface in an RF discharge at a relatively high gas pressure. The wafer surface is then provided with a microscopic roughness by applying a low power so that the inert gas (e.g. argon) ions do not have sufficient energy to etch the surface. A layer of chromium is then sputter deposited on the wafer surface as by a DC magnetron with an intrinsic tensile stress and low gas entrapment by passing a minimal amount of the inert gas through the magnetron and by applying no RF bias to the wafer. The chromium layer is atomically bonded to the microscopically rough wafer surface. A layer of a nickel-vanadium alloy is deposited on the chromium layer and a layer of a metal selected from the group consisting of gold, silver and copper is deposited on the nickel-vanadium layer. The nickel-vanadium layer is deposited between the chromium layer and the metal layer with an intrinsic compressive stress by applying an RF bias to the wafer to neutralize the intrinsic tensile stress of the chromium layer and any intrinsic stress of the metal layer. The electrical component is adhered as by solder to the metal selected from the group consisting of gold, silver and copper.


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