The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 17, 2007

Filed:

Apr. 13, 2004
Applicants:

Se-hoon OH, Chungcheongnam-do, KR;

Jung-hee Chung, Seoul, KR;

Jae-hyoung Choi, Gyeonggi-do, KR;

Jeong-sik Choi, Seoul, KR;

Sung-tae Kim, Seoul, KR;

Cha-young Yoo, Gyeonggi-do, KR;

Inventors:

Se-Hoon Oh, Chungcheongnam-do, KR;

Jung-Hee Chung, Seoul, KR;

Jae-Hyoung Choi, Gyeonggi-do, KR;

Jeong-Sik Choi, Seoul, KR;

Sung-Tae Kim, Seoul, KR;

Cha-Young Yoo, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01);
U.S. Cl.
CPC ...
Abstract

Integrated circuit devices, for example, dynamic random access memory (DRAM) devices, are provided including an integrated circuit substrate having a cell array region and a peripheral circuit region. A buried contact plug is provided on the integrated circuit substrate in the cell array region and a resistor is provided on the integrated circuit substrate in the peripheral circuit region. A first pad contact plug is provided on the buried contact plug in the cell array region and a second pad contact plug is provided on the resistor in the peripheral circuit region. An ohmic layer is provided between the first pad contact plug and the buried contact plug and between the second pad contact plug and the resistor. Related methods of fabricating integrated circuit devices are also provided.


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