The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 10, 2007

Filed:

Jun. 07, 2006
Applicants:

Hideharu Yahata, Inagi, JP;

Masashi Horiguchi, Koganei, JP;

Yoshikazu Saitoh, Hamura, JP;

Yasushi Kawase, Tachikawa, JP;

Inventors:

Hideharu Yahata, Inagi, JP;

Masashi Horiguchi, Koganei, JP;

Yoshikazu Saitoh, Hamura, JP;

Yasushi Kawase, Tachikawa, JP;

Assignees:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 8/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, when instructions for a memory operation for reading memory information from each of memory cells each requiring a refresh operation for periodically holding the memory information, or writing the same therein is issued, carries out an addressing-based autonomous refresh operation different from the memory operation before or after the memory operation. The pseudo static RAM includes address signal transition detectors for a row and a column, and a page mode which independently performs a column address selecting operation according to an address signal transition detect signal of the second address signal transition detector.


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