Fast reading, low consumption memory device and reading method thereof

Abstract

A memory device having a reading configuration and including a plurality of memory cells, arranged in rows and columns, memory cells arranged on the same column having respective first terminals connected to a same bit line and memory cells arranged on the same row having respective second terminals selectively connectable to a same word line; a supply line providing a supply voltage; a column addressing circuit and a row addressing circuit for respectively addressing a bit line and a word line corresponding to a memory cell selected for reading in the reading configuration. The column addressing circuit is configured to bias the addressed bit line corresponding to the selected memory cell substantially at the supply voltage in the reading configuration. A row driving circuit biases the addressed word line corresponding to the selected memory cell at a non-zero word line read voltage, so that a predetermined cell voltage, lower than a phase change voltage, is applied between the first terminal and the second terminal of the selected memory cell in the reading configuration.