Process for locating, displaying, analyzing, and optionally monitoring potential transient defect sites in one or more integrated circuit chips of a semiconductor substrate

Abstract

A process which addresses the problem of transient defects comprises first processing one or more test chips on a substrate to reveal one or more potential transient defects during subsequent processing of all of the chips on the substrate; identifying the exact locations of such potential transient defects on one or more chips of a silicon substrate; forming a file containing the coordinates of each potential transient defect on the chip; converting the file into a CAD image layer capable of displaying such potential transient defects; and displaying such potential transient defects superimposed over a CAD image of the actual circuit to permit visual inspection of the compound CAD image and to permit optional action to be taken in view of such potential transient defects. In another embodiment of the invention, the file containing the locations of the potential transient defects is transmitted to a metrology apparatus such as a critical dimension (CD) scanning electron microscope (SEM) which monitors the potential transient defect addresses during processing of the chip. The two embodiments of the invention may be practiced in the alternative or in combination with one another.