The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 03, 2007
Filed:
Jul. 06, 2006
William C. Plants, Sunnyvale, CA (US);
Arunangshu Kundu, San Jose, CA (US);
William C. Plants, Sunnyvale, CA (US);
Arunangshu Kundu, San Jose, CA (US);
Actel Corporation, Mountain View, CA (US);
Abstract
A method of forming a field programmable gate array architecture having a plurality of input/output pads comprising: providing a plurality of logic clusters; providing a plurality of input/output clusters; providing a plurality of input/output buffers; providing a plurality of dedicated input/output first-in/first-out memory blocks, the dedicated input/output first-in/first-out memory blocks having a first-in/first-out memory coupled to one of the plurality of input/output pads; providing an input/output block controller programmably coupled to the plurality of dedicated input/output first-in/first-out memory blocks, wherein the input/output block controller comprises a dedicated FIFO flag logic block and an input/output FIFO block controller cluster; and providing a routing interconnect architecture programmably coupling the logic clusters, the input/output buffers and the input/output clusters, wherein the dedicated input/output first-in/first-out memory blocks are programmably coupled between the input/output buffers and the input/output clusters.