The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 03, 2007
Filed:
Sep. 04, 2002
Jeff R. Wienrich, Gilbert, AZ (US);
Joni G. Hansen, Phoenix, AZ (US);
Debendra Mallik, Chandler, AZ (US);
Jeff R. Wienrich, Gilbert, AZ (US);
Joni G. Hansen, Phoenix, AZ (US);
Debendra Mallik, Chandler, AZ (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Apparatus and methods are provided to enable circuit configuration of a substrate by the setting of settable bits associated with those circuits. An electrically conductive material is deposited onto selected settable bits which closes the desired circuit between the settable bits. In one embodiment in accordance with the invention, a carrier substrate is provided that comprises settable bits which are used to control a microelectronic package's electrical characteristics. In one embodiment, the settable bits are in the form of sets of spaced-apart bit pads which form an open circuit between a logic circuit and electrical ground (Vss). The open circuit is closed with the application of electrically conductive material that bridges the set of spaced-apart bit pads. The settable bits, therefore, do not require the addition of high profile components such as 0-ohm resisters to form the electrical bridging function between the bit pads of a settable bit. The settable bits provide a highly configurable control interface that allows the setting of one or more electrical characteristics. The settable bits are easily and quickly configurable and do not require complex customized machinery for implementation. Further, they do not significantly add to the cost of development or manufacture of the carrier substrate.