The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 27, 2007

Filed:

Sep. 08, 2004
Applicant:

Hirokatsu Niijima, Tokyo, JP;

Inventor:

Hirokatsu Niijima, Tokyo, JP;

Assignee:

Advantest Corporation, R Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); G06F 11/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor test equipment and a timing measuring method for use in the semiconductor test equipment are provided, that can perform simultaneous measurement of timings of defined times between edges in cycles even in a case where a capacity is large as in a test pattern for the semiconductor test equipment or a case where the cycles are away from each other. In order to achieve this, the semiconductor test equipment includes: a data shifting flip-flip for shifting input data with a reference clock of the semiconductor test equipment by a period of one clock, provided in a secondary logical comparison circuit; the first logical comparison and selection circuitfor determining whether timings of the first defined time Ta that is a period between two pre-selected edges are good or not, and outputting a determination result; and the second logical comparison and selection circuitfor determining whether timings of the second defined time Tb that is a period between two pre-selected edges are good or not, and outputting a determination result.


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