The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 20, 2007
Filed:
Feb. 13, 2004
Jonathan R. Fales, South Burlington, VT (US);
Gregory J. Fredeman, Staatsburg, NY (US);
Kevin W. Gorman, Fairfax, VT (US);
Mark D. Jacunski, Colchester, VT (US);
Toshiaki Kirihata, Poughkeepsie, NY (US);
Alan D. Norris, Hinesburg, VT (US);
Paul C. Parries, Wappingers Falls, NY (US);
Matthew R. Wordeman, Kula, HI (US);
Jonathan R. Fales, South Burlington, VT (US);
Gregory J. Fredeman, Staatsburg, NY (US);
Kevin W. Gorman, Fairfax, VT (US);
Mark D. Jacunski, Colchester, VT (US);
Toshiaki Kirihata, Poughkeepsie, NY (US);
Alan D. Norris, Hinesburg, VT (US);
Paul C. Parries, Wappingers Falls, NY (US);
Matthew R. Wordeman, Kula, HI (US);
International Business Machines Corp., Armonk, NY (US);
Abstract
Disclosed is a flexible command multiplication scheme for the built-in-self test (BIST) of a high-speed embedded memory array that segments BIST functionality into remote lower-speed executable instructions and local higher-speed executable instructions. A stand-alone BIST logic controller operates at a lower frequency and communicates with a command multiplier using a low-speed BIST instruction seed set. The command multiplier uses offset or directive registers to drive a logic unit or ALU to generate 'n' sets of CAD information which are then time-multiplexed to the embedded memory at a speed 'n' times faster than the BIST operating speed.