The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 20, 2007
Filed:
Mar. 16, 2005
Nai-chen Peng, Hsin-Chu, TW;
Shui-chin Huang, Tai-Nan, TW;
Tzyh-cheang Lee, Hsin-Chu, TW;
Chuan Fu Wang, Miao-Li County, TW;
Sung-bin Lin, Hsin-Chu, TW;
Nai-Chen Peng, Hsin-Chu, TW;
Shui-Chin Huang, Tai-Nan, TW;
Tzyh-Cheang Lee, Hsin-Chu, TW;
Chuan Fu Wang, Miao-Li County, TW;
Sung-Bin Lin, Hsin-Chu, TW;
United Microelectronics Corp., Hsin-Chu, TW;
Abstract
The single-poly EEPROM includes a first PMOS transistor serially connected to a second PMOS transistor. The first and second PMOS transistors are both formed on an N-well of a P type substrate. The first PMOS transistor includes a floating gate, a first Pdoped drain region and a first Pdoped source region. The second PMOS transistor includes a gate and a second Pdoped source region. The first Pdoped drain region of the first PMOS transistor serves as a drain of the second PMOS transistor. A diode is located in the P type substrate including a P-well and a Ndoped region. The floating gate overlaps with the N-well and extends to the Ndoped region. The overlapped region of the P-well and the Ndoped region junction beneath the floating gate serves as an avalanche injection point in the vicinity of the first PMOS transistor.