The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 13, 2007
Filed:
Aug. 22, 2001
Donald V. Organ, Saratoga, CA (US);
Kenneth J. Lanier, Medway, MA (US);
Roger W. Blethen, Dover, MA (US);
H. Neil Kelly, Westwood, MA (US);
Michael G. Davis, San Jose, CA (US);
Jeffrey H. Perkins, Cambridge, MA (US);
Tommie Berry, Pleasanton, CA (US);
Phillip Burlison, Morgan Hill, CA (US);
Mark Deome, San Jose, CA (US);
Christopher J. Hannaford, South Weymouth, MA (US);
Edward J. Terrenzi, Walpole, MA (US);
David Menis, Cohasset, MA (US);
David W. Curry, Cohasset, MA (US);
Eric Rosenfeld, Ashland, MA (US);
Donald V. Organ, Saratoga, CA (US);
Kenneth J. Lanier, Medway, MA (US);
Roger W. Blethen, Dover, MA (US);
H. Neil Kelly, Westwood, MA (US);
Michael G. Davis, San Jose, CA (US);
Jeffrey H. Perkins, Cambridge, MA (US);
Tommie Berry, Pleasanton, CA (US);
Phillip Burlison, Morgan Hill, CA (US);
Mark Deome, San Jose, CA (US);
Christopher J. Hannaford, South Weymouth, MA (US);
Edward J. Terrenzi, Walpole, MA (US);
David Menis, Cohasset, MA (US);
David W. Curry, Cohasset, MA (US);
Eric Rosenfeld, Ashland, MA (US);
LTX Corporation, Norwood, MA (US);
Abstract
An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patterns to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns. A tester computer supervises the application of digital, analog, and memory test signals from the digital, analog, and memory test circuitry to the device under test such that signals applied to the device under test can be solely digital test signals, solely analog test signals, solely memory test signals, or mixed digital, analog, and memory test signals. The test head, the digital test circuitry, the analog test circuitry, the memory test circuitry, and the computer are operable as a single platform.