The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 13, 2007

Filed:

Oct. 24, 2003
Applicants:

Evan E. Patton, Portland, OR (US);

Theodore Cacouris, Portland, OR (US);

Eliot Broadbent, Beaverton, OR (US);

Steven T. Mayer, Lake Oswego, OR (US);

Inventors:

Evan E. Patton, Portland, OR (US);

Theodore Cacouris, Portland, OR (US);

Eliot Broadbent, Beaverton, OR (US);

Steven T. Mayer, Lake Oswego, OR (US);

Assignee:

Novellus Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods and apparatus are provided for processing semiconductor wafers sequentially. Sequential processes employ multi-station processing modules, where particular encompassing wafer processes are divided into sub-processes, each optimized for increasing wafer to wafer uniformity, result quality, and overall wafer throughput. In one example, a copper electroplating module includes separate stations for wetting, initiation, seed layer repair, fill, overburden, reclaim, and rinse.


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