The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 13, 2007

Filed:

Aug. 31, 2004
Applicants:

Mohammad R. Mirbedini, Redwood City, CA (US);

Venkatesh P. Gopinath, Fremont, CA (US);

Hong Lin, Vancouver, WA (US);

Verne Hornback, Camas, WA (US);

Dodd Defibaugh, Camas, WA (US);

Ynhi Le, Gresham, OR (US);

Inventors:

Mohammad R. Mirbedini, Redwood City, CA (US);

Venkatesh P. Gopinath, Fremont, CA (US);

Hong Lin, Vancouver, WA (US);

Verne Hornback, Camas, WA (US);

Dodd Defibaugh, Camas, WA (US);

Ynhi Le, Gresham, OR (US);

Assignee:

LSI Logic Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/461 (2006.01);
U.S. Cl.
CPC ...
Abstract

Dual trench depths are achieved on the same wafer by forming an initial trench having a depth corresponding to the difference in final depths of the shallow and deep trenches. A second mask is used to open areas for the deep trenches over the preliminary trenches and for the shallow trenches at additional locations. Etching of the shallow and deep trenches then proceeds simultaneously.


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