The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 27, 2007

Filed:

May. 26, 2005
Applicants:

Lan-ting Huang, Hsin-Chu, TW;

Chen-chin Liu, Hsin-Chu, TW;

Cheng Jye Liu, Jhongli, TW;

Inventors:

Lan-Ting Huang, Hsin-Chu, TW;

Chen-Chin Liu, Hsin-Chu, TW;

Cheng Jye Liu, Jhongli, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/792 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor memory device structure includes an isolation region formed along an edge of a memory cell portion adjacent to a dummy cell portion to isolate the memory cell portion from leakage current generated in the dummy cell portion.


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Huang, Lan-Ting. (2007). Memory array including isolation between memory cell and dummy cell portions (U.S. Patent No. 7183608). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7183608

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