The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 27, 2007

Filed:

Jun. 02, 2004
Applicants:

Yong-jin Kim, Suwon-si, KR;

Kyeong-koo Chi, Seoul, KR;

Chang-jin Kang, Suwon-si, KR;

Hyoung-sub Kim, Yongin-si, KR;

Myeong-cheol Kim, Suwon-si, KR;

Tae-rin Chung, Gunpo-si, KR;

Sung-hoon Chung, Suwon-si, KR;

Ji-young Kim, Yongin-si, KR;

Inventors:

Yong-Jin Kim, Suwon-si, KR;

Kyeong-Koo Chi, Seoul, KR;

Chang-Jin Kang, Suwon-si, KR;

Hyoung-Sub Kim, Yongin-si, KR;

Myeong-Cheol Kim, Suwon-si, KR;

Tae-Rin Chung, Gunpo-si, KR;

Sung-Hoon Chung, Suwon-si, KR;

Ji-Young Kim, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device includes a plurality of gate trenches, each of which has first inner walls, which face each other in a first direction which is perpendicular to a second direction in which active regions extend, and second inner walls, which face each other in the second direction in which the active regions extends. An isolation layer contacts a gate insulating layer throughout the entire length of the first inner walls of the gate trenches including from entrance portions of the gate trenches to bottom portions of the gate trenches, and a plurality of channel regions are disposed adjacent to the gate insulating layers in the semiconductor substrate along the second inner walls and the bottom portions of the gate trenches.


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