The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 20, 2007
Filed:
Feb. 02, 2005
Masahiro Murata, Tokyo, JP;
Yusuke Nagai, Tokyo, JP;
Yukio Morishige, Tokyo, JP;
Satoshi Kobayashi, Tokyo, JP;
Naoki Ohmiya, Tokyo, JP;
Masahiro Murata, Tokyo, JP;
Yusuke Nagai, Tokyo, JP;
Yukio Morishige, Tokyo, JP;
Satoshi Kobayashi, Tokyo, JP;
Naoki Ohmiya, Tokyo, JP;
Disco Corporation, Tokyo, JP;
Abstract
A method of dividing, along dividing lines, a wafer having function elements formed in areas sectioned by the dividing lines formed in a lattice pattern on the front surface, which comprises: a protective member affixing step for affixing a protective member to the front surface of the wafer; a polishing step for polishing the back surface of the wafer having the protective member affixed to the front surface; a deteriorated layer formation step for forming a deteriorated layer along the dividing lines in the inside of the wafer by applying a pulse laser beam capable of passing through the wafer to the wafer along the dividing lines from the polished back surface side of the wafer; a frame holding step for affixing the back surface of the wafer in which the deteriorated layers have been formed along the dividing lines, to a dicing tape mounted on an annular frame; a dividing step for dividing the wafer into individual chips along the dividing lines by exerting external force along the dividing lines where the deteriorated layers have been formed, of the wafer held on the frame; an expansion step for enlarging the interval between chips by stretching the dicing tape affixed to the wafer divided into individual chips; and a pick up step for picking up the chips from the stretched dicing tape.