The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 13, 2007
Filed:
Jan. 23, 2004
Tsukio Funaki, Ebina, JP;
Tsukio Funaki, Ebina, JP;
Renesas Technology Corp., Tokyo, JP;
Renesas Eastern Japan Semiconductor, Inc., Tokyo, JP;
Abstract
Provided is a semiconductor device having a semiconductor chip mounted over a substrate, in which an interconnect is formed, by using an adhesive layer to permit contact conduction between a stud bump of the semiconductor chip and an interconnect of a tape substrate, wherein an adhesive layer formed integral as a film is adhered to each block made of substrates corresponding to a plurality of semiconductor devices and contact bonding under heat is conducted. The adhesive layer corresponding to the plurality of semiconductor devices is thus formed continuously and with this adhesive layer, the interconnect formation surface at the end portion of the substrate is covered. Moreover, with a thermosetting resin used as the adhesive layer, the semiconductor chip and substrate are adhered by contact bonding under heat while placing the substrate on a rigid heat insulating plate. According to the present invention, heat diffusion and deformation of the substrate upon contact bonding under heat can be prevented by the rigid heat insulating plate. Upon dicing, the peeling of the interconnect from the substrate can be prevented by holding the interconnect with the adhesive layer at the end portion of the substrate.