The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 30, 2007
Filed:
Jul. 02, 1999
Manpreet S. Khaira, Portland, OR (US);
Steve W. Otto, Portland, OR (US);
Honghua H. Yang, Portland, OR (US);
Mandar S. Joshi, Aloha, OR (US);
Jeremy S. Casas, Portland, OR (US);
Erik M. Seligman, Beaverton, OR (US);
Manpreet S. Khaira, Portland, OR (US);
Steve W. Otto, Portland, OR (US);
Honghua H. Yang, Portland, OR (US);
Mandar S. Joshi, Aloha, OR (US);
Jeremy S. Casas, Portland, OR (US);
Erik M. Seligman, Beaverton, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A method of preparing a circuit model for simulation comprises decomposing the circuit model having a number of latches into a plurality of extended latch boundary components and partitioning the plurality of extended latch boundary components. Decomposing and partitioning the circuit model may include decomposing hierarchical cells of the circuit model, and using a constructive bin-packing heuristic to partition the plurality of extended latch boundary components. The partitioned circuit model is compiled, and simulated on a uni-processor, a multi-processor, or a distributed processing computer system.