The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7167397 B1

PDF
Full Text
Expired
Date of Patent:
Jan. 23, 2007

Filed:

Jun. 21, 2005
Applicants:

Fabrice Paillet, Hillsboro, OR (US);

Ali Keshavarzi, Portland, OR (US);

Muhammad M. Khellah, Tigard, OR (US);

Dinesh Somasekhar, Portland, OR (US);

Yibin YE, Portland, OR (US);

Stephen H. Tang, Pleasanton, CA (US);

Mohsen Alavi, Portland, OR (US);

Vivek K. DE, Beaverton, OR (US);

Tanay Karnik, Portland, OR (US);

Inventors:

Fabrice Paillet, Hillsboro, OR (US);

Ali Keshavarzi, Portland, OR (US);

Muhammad M. Khellah, Tigard, OR (US);

Dinesh Somasekhar, Portland, OR (US);

Yibin Ye, Portland, OR (US);

Stephen H. Tang, Pleasanton, CA (US);

Mohsen Alavi, Portland, OR (US);

Vivek K. De, Beaverton, OR (US);

Tanay Karnik, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of programming a memory array is provided, including accessing a plurality of word lines of the memory array by providing a plurality of voltage steps sequentially after one another to the respective word lines, and accessing a plurality of bit lines of the memory array each time that a respective word line is accessed, to program a plurality of devices corresponding to individual word and bit lines that are simultaneously accessed, each device being programmed by breaking a dielectric layer of the device, accessing of the bit lines being sequenced such that only a single one of the devices is programmed at a time.


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