The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 23, 2007
Filed:
Feb. 03, 2004
Jason P. Gill, Essex Junction, VT (US);
Terence B. Hook, Jericho, VT (US);
Randy W. Mann, Poughquag, NY (US);
William J. Murphy, North Ferrisburgh, VT (US);
William R. Tonti, Essex Junction, VT (US);
Steven H. Voldman, South Burlington, VT (US);
Jason P. Gill, Essex Junction, VT (US);
Terence B. Hook, Jericho, VT (US);
Randy W. Mann, Poughquag, NY (US);
William J. Murphy, North Ferrisburgh, VT (US);
William R. Tonti, Essex Junction, VT (US);
Steven H. Voldman, South Burlington, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method and system for forming a semiconductor device having superior ESD protection characteristics. A resistive material layer is disposed within a contact hole on at least one of the contact stud upper and lower surface. In preferred embodiments, the integral resistor has a resistance value of between about one Ohm and about ten Ohms, or between 10 and 100 Ohms. Embodiments of the resistive layer include sputtered silicon material, a tunnel oxide, a tunnel nitride, a silicon-implanted oxide, a silicon-implanted nitride, or an amorphous polysilicon. Embodiments of the invention include SRAMs, bipolar transistors, SOI lateral diodes, MOSFETs and SiGe Transistors.