The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 23, 2007

Filed:

Oct. 04, 2004
Applicants:

Diane C. Boyd, LaGrangeville, NY (US);

Hussein I. Hanafi, Basking Ridge, NJ (US);

Erin C. Jones, Tuckahoe, NY (US);

Dominic J. Schepis, Wappingers Falls, NY (US);

Leathen Shi, Yorktown Heights, NY (US);

Inventors:

Diane C. Boyd, LaGrangeville, NY (US);

Hussein I. Hanafi, Basking Ridge, NJ (US);

Erin C. Jones, Tuckahoe, NY (US);

Dominic J. Schepis, Wappingers Falls, NY (US);

Leathen Shi, Yorktown Heights, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/30 (2006.01); H01L 21/46 (2006.01); H01L 21/21 (2006.01); H01L 21/36 (2006.01); H01L 21/425 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of fabricating a SOI wafer having a gate-quality, thin buried oxide region is provided. The wafer is fabricating by forming a substantially uniform thermal oxide on a surface of a Si-containing layer of a SOI substrate which includes a buried oxide region positioned between the Si-containing layer and a Si-containing substrate layer. Next, a cleaning process is employed to form a hydrophilic surface on the thermal oxide. A carrier wafer having a hydrophilic surface is provided and positioned near the substrate such that the hydrophilic surfaces adjoin each other. Room temperature bonding is then employed to bond the carrier wafer to the substrate. An annealing step is performed and thereafter, the Si-containing substrate of the silicon-on-insulator substrate and the buried oxide region are selectively removed to expose the Si-containing layer.


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