The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 23, 2007
Filed:
Oct. 30, 2003
Masayuki Furuhashi, Kawasaki, JP;
Toshifumi Mori, Kawasaki, JP;
Young Suk Kim, Kawasaki, JP;
Takayuki Ohba, Kawasaki, JP;
Ryou Nakamura, Kawasaki, JP;
Masayuki Furuhashi, Kawasaki, JP;
Toshifumi Mori, Kawasaki, JP;
Young Suk Kim, Kawasaki, JP;
Takayuki Ohba, Kawasaki, JP;
Ryou Nakamura, Kawasaki, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
The semiconductor device fabrication method comprises the step of forming gate electrodeon a semiconductor substratewith a gate insulation filmformed therebetween; the step of implanting dopants in the semiconductor substratewith the gate electrodeas the mask to form dopant diffused regions; the step of forming a silicon oxide filmon the semiconductor substrate, covering the gate electrodes; anisotropically etching the silicon oxide filmto form sidewall spacersincluding the silicon oxide filmon the side walls of the gate electrode. In the step of forming a silicon oxide film, the silicon oxide filmis formed by thermal CVD at a 500–580° C. film forming temperature, using bis(tertiary-butylamino)silane and oxygen as raw materials. Silicon oxide filmis formed at a relatively low film forming temperature, whereby the diffusion of the dopant in the doapnt diffused regionsforming the shallow region of the extension source/drain structure can be suppressed.