The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 16, 2007

Filed:

Aug. 28, 2003
Applicants:

Jyunichi Nakamura, Nagano, JP;

Tadashi Kodaira, Nagano, JP;

Shunichiro Matsumoto, Nagano, JP;

Hironari Aratani, Nagano, JP;

Takanori Tabuchi, Nagano, JP;

Takeshi Chino, Nagano, JP;

Inventors:

Jyunichi Nakamura, Nagano, JP;

Tadashi Kodaira, Nagano, JP;

Shunichiro Matsumoto, Nagano, JP;

Hironari Aratani, Nagano, JP;

Takanori Tabuchi, Nagano, JP;

Takeshi Chino, Nagano, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H05K 3/46 (2006.01); H05K 3/34 (2006.01); H05K 1/00 (2006.01); H10L 23/12 (2006.01);
U.S. Cl.
CPC ...
Abstract

A multilayered substrate for a semiconductor device, which has a multilayered substrate body formed of a plurality sets of a conductor layer and an insulation layer, and having a face for mounting a semiconductor element thereon and another face for external connection terminals, the face for mounting a semiconductor device being provided with pads through which the substrate is connected to a semiconductor element to be mounted thereon, and the face for external connection terminals being provided with pads through which the substrate is connected to an external electrical circuit, wherein a reinforcing sheet is respectively joined to the face for mounting a semiconductor element thereon and the face for external connection terminals of the multilayered substrate body.


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