The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 09, 2007

Filed:

Jul. 05, 2005
Applicants:

Shian-jyh Lin, Chiayi Hsien, TW;

Sheng-tsung Chen, Tainan, TW;

Neng-tai Shih, Taipei, TW;

Chien-chang Huang, Taipei, TW;

Chien-jung Yang, Taoyuan, TW;

Yi-jung Chen, Taipei, TW;

Inventors:

Shian-Jyh Lin, Chiayi Hsien, TW;

Sheng-Tsung Chen, Tainan, TW;

Neng-Tai Shih, Taipei, TW;

Chien-Chang Huang, Taipei, TW;

Chien-Jung Yang, Taoyuan, TW;

Yi-Jung Chen, Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/4763 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of fabricating a MOS transistor by millisecond annealing. A semiconductor substrate with a gate stack comprising a gate electrode overlying a gate dielectric layer on a top surface of a semiconductor substrate is provided. At least one implanting process is performed to form two doped regions on opposite sides of the gate electrode. Millisecond annealing activates dopants in the doped regions. The millisecond anneal includes rapid heating and rapid cooling within 1 to 50 milliseconds.


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