The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 26, 2006
Filed:
Jan. 30, 2004
Hiroyuki Yamashita, Yokohama, JP;
Takao Shinsha, Yokohama, JP;
Hideaki Fujikake, Fukuoka, JP;
Toshiaki Kowatari, Oume, JP;
Tomoya Hirao, Machida, JP;
Atsushi Ohkuma, Kashiwa, JP;
Hiroaki Nishi, Yokohama, JP;
Michiaki Muraoka, Machida, JP;
Hiroyuki Yamashita, Yokohama, JP;
Takao Shinsha, Yokohama, JP;
Hideaki Fujikake, Fukuoka, JP;
Toshiaki Kowatari, Oume, JP;
Tomoya Hirao, Machida, JP;
Atsushi Ohkuma, Kashiwa, JP;
Hiroaki Nishi, Yokohama, JP;
Michiaki Muraoka, Machida, JP;
Seiko Epson Corporation, Tokyo, JP;
Abstract
A hardware/software co-verification method that achieves fast simulation execution by implementing a C-based native code simulation without degrading the accuracy of timing verification. This method is a method for co-verifying hardware and software, by using a host CPU, for a semiconductor device on which at least one target CPU and one OS are mounted wherein, first, a timed software component described in a C-based language or constructed from binary code native to the host CPU and a hardware component described in the C-based language are input as verification models, necessary compiling is performed, and the compiled components are linked together. Next, a testbench is input and compiled. Then, the components and the testbench are linked together, after which simulation is performed and the result of the simulation is output.