The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 12, 2006
Filed:
May. 11, 2004
Andrew F. Glew, Hillsboro, OR (US);
Larry M. Mennemeier, Boulder Creek, CA (US);
Alexander D. Peleg, Haifa, IL;
David Bistry, Cupertino, CA (US);
Millind Mittal, South San Francisco, CA (US);
Carole Dulong, Saratoga, CA (US);
Eiichi Kowashi, Ibaraki, JP;
Benny Eitan, Haifa, IL;
Derrik Lin, Foster City, CA (US);
Romamohan R. Vakkalagadda, Fremont, CA (US);
Andrew F. Glew, Hillsboro, OR (US);
Larry M. Mennemeier, Boulder Creek, CA (US);
Alexander D. Peleg, Haifa, IL;
David Bistry, Cupertino, CA (US);
Millind Mittal, South San Francisco, CA (US);
Carole Dulong, Saratoga, CA (US);
Eiichi Kowashi, Ibaraki, JP;
Benny Eitan, Haifa, IL;
Derrik Lin, Foster City, CA (US);
Romamohan R. Vakkalagadda, Fremont, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A processor with instructions to operate on different data types stored in a single logical register file. According to one embodiment of the invention, a processor includes a number of physical registers, a memory unit, and a decode/execution unit. The memory unit is to make the number of physical registers appear to software as a single software-visible register file. The decode/execution unit is to execute on the contents of the single software-visible register file instructions of a first instruction type and of a second instruction type, wherein the single software-visible register file is to be operated as a flat register file during execution of instructions of the second instruction type and as a stack referenced register file during execution of instructions of the first instruction type.