The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 12, 2006

Filed:

Mar. 20, 2002
Applicants:

Mitsuru Oida, Kanagawa-ken, JP;

Masatoshi Fukuda, Kanagawa-ken, JP;

Yasuhiro Koshio, Kanagawa-ken, JP;

Hiroshi Funakura, Kanagawa-ken, JP;

Inventors:

Mitsuru Oida, Kanagawa-ken, JP;

Masatoshi Fukuda, Kanagawa-ken, JP;

Yasuhiro Koshio, Kanagawa-ken, JP;

Hiroshi Funakura, Kanagawa-ken, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 31/72 (2006.01); H01L 27/15 (2006.01); H01L 29/788 (2006.01); H01L 31/232 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor package includes (a) an interposer, (b) a wiring layer containing conductors formed adjacent to each other at intervals that cause no short circuit among the conductors, the wiring layer covering a given area of the interposer, to block light from passing through the given area, (c) a light blocking layer covering a no-wiring area of the interposer not covered by the wiring layer, to block light from passing through the no-wiring area, (d) a semiconductor chip electrically connected to the wiring layer, and (e) a resin mold sealing the wiring layer, the light blocking layer, and the semiconductor chip.


Find Patent Forward Citations

Loading…