The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 05, 2006
Filed:
Jul. 24, 2002
Naohiko Hirano, Okazaki, JP;
Takanori Teshima, Okazaki, JP;
Yoshimi Nakase, Anjo, JP;
Kenji Yagi, Okazaki, JP;
Yasushi Ookura, Toyokawa, JP;
Kuniaki Mamitsu, Okazaki, JP;
Kazuhito Nomura, Okazaki, JP;
Yutaka Fukuda, Kariya, JP;
Naohiko Hirano, Okazaki, JP;
Takanori Teshima, Okazaki, JP;
Yoshimi Nakase, Anjo, JP;
Kenji Yagi, Okazaki, JP;
Yasushi Ookura, Toyokawa, JP;
Kuniaki Mamitsu, Okazaki, JP;
Kazuhito Nomura, Okazaki, JP;
Yutaka Fukuda, Kariya, JP;
Denso Corporation, Kariya, JP;
Abstract
A semiconductor device includes a semiconductor chip that generates heat in operation, a pair of heat sinks for cooling the chip, and a mold resin, in which the chip and the heat sinks are embedded. The thickness tof the chip and the thickness tof one of heat sinks that is joined to the chip using a solder satisfy the equation of t/t≧5. Furthermore, the thermal expansion coefficient αof the heat sinks and the thermal expansion coefficient αof the mold resin satisfy the equation of 0.5≦α≦1.5. In addition, the surface of the chip that faces the solder has a roughness Ra that satisfies the equation of Ra≦500 nm. Moreover, the solder is a Sn-based solder to suppress relaxation of a compressive stress in the chip, which is caused by the creeping of the solder.