The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 28, 2006
Filed:
Aug. 08, 2002
Applicants:
Jason H. Anderson, Toronto, CA;
Sudip K. Nag, San Jose, CA (US);
Guenter Stenz, Campbell, CA (US);
Srinivasan Dasasathyan, Sunnyvale, CA (US);
Inventors:
Jason H. Anderson, Toronto, CA;
Sudip K. Nag, San Jose, CA (US);
Guenter Stenz, Campbell, CA (US);
Srinivasan Dasasathyan, Sunnyvale, CA (US);
Assignee:
Xilinx, Inc., San Jose, CA (US);
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 9/45 (2006.01);
U.S. Cl.
CPC ...
Abstract
Application of network flow techniques to constrained optimization problems is disclosed. The present of constrains may lead to infeasible solutions. The infeasible solutions can be removed by an iterative process of changing the structure of the network and/or the associated parameters. Specific applications of the invention to the placement of tristate buffers and clocks in integrated circuits are disclosed.