The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7141474 B1

PDF
Full Text
Expired
Date of Patent:
Nov. 28, 2006

Filed:

Dec. 10, 2004
Applicants:

Masayuki Ichige, Yokohama, JP;

Koji Hashimoto, Yokohama, JP;

Tatsuaki Kuji, Fukaya, JP;

Seiichi Mori, Ohta-ku, JP;

Riichiro Shirota, Fujisawa, JP;

Yuji Takeuchi, Yokohama, JP;

Koji Sakui, Setagaya-ku, JP;

Inventors:

Masayuki Ichige, Yokohama, JP;

Koji Hashimoto, Yokohama, JP;

Tatsuaki Kuji, Fukaya, JP;

Seiichi Mori, Ohta-ku, JP;

Riichiro Shirota, Fujisawa, JP;

Yuji Takeuchi, Yokohama, JP;

Koji Sakui, Setagaya-ku, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of fabricating a nonvolatile semiconductor memory including the steps of: sequentially forming a gate insulating layer and a first conductive layer of a floating gate on a semiconductor substrate; depositing an inter-gate insulating layer; forming an opening in a part of the inter-gate insulating layer; depositing a control gate electrode on the inter-gate insulating layer and an exposed portion of the first conductive layer by the opening; and forming the gate electrodes of the memory cell transistors and the gate electrodes of the select transistors by utilizing the etching processes of the control gate electrode, the inter-gate insulating layer and the first conductive layer, wherein the select transistors include at least a part of the exposed portion of the first conductive layer.


Find Patent Forward Citations

Ichige, Masayuki. (2006). Fabrication method of a nonvolatile semiconductor memory (U.S. Patent No. 7141474). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7141474

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