The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 21, 2006
Filed:
Jun. 30, 2003
Bruce Querbach, Orangevale, CA (US);
David G. Ellis, Tualatin, OR (US);
Amjad Khan, Folsom, CA (US);
Michael J. Tripp, Forest Grove, OR (US);
Eric S. Gayles, Folsom, CA (US);
Eshwar Gollapudi, Folsom, CA (US);
Bruce Querbach, Orangevale, CA (US);
David G. Ellis, Tualatin, OR (US);
Amjad Khan, Folsom, CA (US);
Michael J. Tripp, Forest Grove, OR (US);
Eric S. Gayles, Folsom, CA (US);
Eshwar Gollapudi, Folsom, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A multi-bit test value is loaded into a built-in latch of the IC component, and a pad of the component is selected for testing. A number of different sequences of test values are automatically generated, based on the stored test value, without scanning-in additional multi-bit values into the latch. A signal that is based on the different sequences of test values is driven into the selected pad and looped back. A difference between the test values and the looped back version of the test values is determined, while automatically adjusting driver and/or receiver characteristics to determine a margin of operation of on-chip I/O buffering for the selected pad.