The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 21, 2006

Filed:

Nov. 07, 2005
Applicants:

Shigeo Moriyama, Tama, JP;

Yoshihiro Ishida, Hitachinaka, JP;

Takashi Kugaya, Hitachinaka, JP;

Shigeo Ootsuki, Kasama, JP;

Soichi Katagiri, Kodaira, JP;

Sadayuki Nishimura, Yokohama, JP;

Ryosei Kawai, Kodaira, JP;

Kan Yasui, Kokubunji, JP;

Inventors:

Shigeo Moriyama, Tama, JP;

Yoshihiro Ishida, Hitachinaka, JP;

Takashi Kugaya, Hitachinaka, JP;

Shigeo Ootsuki, Kasama, JP;

Soichi Katagiri, Kodaira, JP;

Sadayuki Nishimura, Yokohama, JP;

Ryosei Kawai, Kodaira, JP;

Kan Yasui, Kokubunji, JP;

Assignee:

Hitachi Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B24B 49/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention relates to a polishing apparatus, and a semiconductor manufacturing method using the apparatus. Dressing of a grindstone surface is ground by sizing processing whereby dressing of a tool surface can be done while preventing occurrence of cracks on the grindstone surface which is the cause for occurrence of scratches. Further, flatness of the surface of a dressing tool can be guaranteed because of sizing cutting-in; even if a thick grindstone of a few centimeters is used, the flatness can be maintained to the end; and processing with less in-face unevenness can be always carried out. Therefore, the life of the dressing tool can be greatly extended. Further, the present sizing-dressing is carried out jointly with processing of a wafer to thereby enable improvement of throughput of the apparatus as well as maintenance of a processing rate. The present apparatus and method are effective for planarization of various substrate surfaces having irregularities.


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