The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 14, 2006

Filed:

Feb. 17, 2004
Applicants:

Youval Nehmadi, Modiin, IL;

Josephine Phua, San Jose, CA (US);

Jacob Joseph Orbon, Jr., Morgan Hill, CA (US);

Ariel Ben-porath, Gealya, IL;

Evgeny Levin, Cupertino, CA (US);

Ofer Bokobza, Cupertino, CA (US);

Inventors:

Youval Nehmadi, Modiin, IL;

Josephine Phua, San Jose, CA (US);

Jacob Joseph Orbon, Jr., Morgan Hill, CA (US);

Ariel Ben-Porath, Gealya, IL;

Evgeny Levin, Cupertino, CA (US);

Ofer Bokobza, Cupertino, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/66 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for monitoring fabrication of an integrated circuit (IC) on a semiconductor wafer includes generating a product design profile (PDP) using an electronic design automation (EDA) tool, the PDP comprising an indication of a site in at least one layer of the IC that is susceptible to a process fault. Upon fabricating at least one layer of the IC on the wafer, a process monitoring tool is applied to perform a measurement at the site in at least one layer responsively to the PDP.


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